Such switchable elements may take the form of spatial light modulators which spatially modulate light from a light source, the spatially modulated light being projected onto a display screen to produce a displayed image. Examples of spatial light modulators include deflectable mirror devices as, for example, described in "Deformable Mirror Spatial Light Modulators" by Hornbeck, published in the Proceedings of SPIE, Vol. 1150, August 1989. Such deflectable or "deformable" mirror devices (DMDs) include an array of switchable mirror devices, each mirror device being mounted on a torsion element over a control electrode. Applying an electric field between each mirror device and the electrode causes the mirror device to pivot, thus changing the direction of light reflected from the mirror device.
Another example of a spatial light modulator is a liquid crystal device.
Alternatively, the matrix array of switchable elements may take the form of an array of light sources which themselves can be switched either "on" or "off", as for example in an array of light emitting diodes.
Generally such display devices are digital devices, that is each switchable element of the display device is effective to switch the light passing from the element to the displayed image either "on" or "off" so as to produce either "white" or "black" pixels on the displayed image. It is, however, possible to display grey scale images by controlling the time for which each switchable element of the display device is in a state such that light from the element arrives at the displayed image, and using the integrating response of the eye of an observer who will perceive a grey scale image from the element.
An example of such an arrangement is described in GB 2014822 which discloses a display device incorporating an X-Y array of energizable light emitting devices. The display device described in GB 2014822 takes data in binary digital forms, for example via an 8 bit signal, the device being driven a line at a time in a number of periods during which the modulators may be "on" or "off". The "ton"/"off" state of each pixel during each time period is determined by the state of the corresponding bit of the digital input data.
Display devices incorporating spatial light modulators, for example in the form of deflectable mirror devices, operate in an analogous manner. In deflectable mirror devices, however, the entire pixel array is driven simultaneously in sympathy with the video source vertical scan rate.
For an 8-bit input video signal, the eight time periods within each display frame period are of different lengths corresponding to bits D0 to D7 of the input video signal. The length of the time period corresponding to the least significant bit (LSB) or D0 in the input signal for any particular frame is set at a predetermined value, the duration of the time period corresponding to the next to the least significant bit (D1) being twice as long as that corresponding to the LSB, and so on. Thus, the length of the time period corresponding to the most significant bit (MSB) or D7 in the input signal is 128 times that corresponding to the LSB. Provided that all the time periods are included within a display frame period of less than around 20 msecs duration, the eye of the observer will integrate the periods and respond as if to a single period having a level of brightness corresponding to the binary signal value. All the bits of the same significance are entered into the element of the array effectively simultaneously. At the end of each sub-frame period corresponding to a single bit of the input signal, a single reset signal is supplied to all the elements of the array simultaneously in order to switch the elements either into a rest position in some systems as for example described in our copending application WO 92/12506, or into the state determined by the next bit signal in other systems.
When the single bit data for all mirror elements is loaded into the DMD and displayed in a single mirror reset cycle operation, then any bit significances requiring a display time of less then this single bit data load time cannot support loading of the next data bit before it itself needs to be terminated. In this situation, loading of the next data bit can only be achieved by first setting the mirrors to the display "off" state at the end of the current display time, and only then starting to load the next data bit. Thus whilst the next data bit is loading, the projector has no useful display light output and is optically dead. This optical dead time results in a loss of optical efficiency.
In U.S. Pat. No. 5,673,060 (the contents of which are incorporated herewith by reference, there is described a method whereby the mirror elements are divided into individually resettable groups. Thus in a "split reset" drive system, the mirror element matrix is divided into blocks of N individually resettable rows, columns, or diagonals with corresponding rows, columns, or diagonals from each block being connected to the same reset line. The individual mirror rows, columns, or diagonals within each block can be loaded with data in any order and can have different bit weight sequences for each row, column, or diagonal. The timing of the loading is such that the duration from loading a given row, column, or diagonal from the first data bit to loading the same row, column, or diagonal with the next data bit is proportional to the significance of the first data bit.
In a practical deflectable mirror device, the data applied to the mirror element address electrodes is stored in a CMOS data latch fabricated in an underlying silicon substrate. Operating with a mirror bias voltage as described, for example in the Hornbeck article cited herebefore such that the mirror elements retain their angle of tilt independent of the address electrode status until the next reset signal is applied, the CMOS latches for the rows not currently being loaded serve only a passive role in the data load/mirror reset cycle. Thus, with such a split reset mirror drive system, it is possible to share a single row of latches between the N mirror row, columns, or diagonals such that the active reset line then determines which row, column, or diagonal of mirror (elements is updated from the CMOS data latch. This brings about a benefit in that a reduced number of active devices is required from which to fabricate the CMOS latches, and hence an improved substrate yield is achieved according to established rules of semiconductor fabrication.
A further advantage of such a split reset system is that for a block of N individually addressable rows, columns, or diagonals, then only one Nth of the single bit frame of data needs to be loaded at any one time. This amount of data can be loaded in one Nth the time of the total single bit data for a non-split reset system. Thus shorter basic bit intervals can be displayed, without the need for a data load dead time cycle during which the mirror displays "black" whilst the next bit data is loaded into the substrate latches. Thus, split reset offers the opportunity to improve the overall optical modulation efficiency by reducing the amount of data load dead time required.
Conversely, a disadvantage of such a split reset mirror addressing scheme is that there is additional scope for image artefact generation as described in our co-pending international patent application GB93/02129. These artefacts arise as a result of relative motion between the displayed image and the observer interacting with the temporal displacements between displayed bit intervals of the same bit significance on nearby pixels. Where split reset is used, this results in the appearance of so-called "scalloping" artefacts running along lines displayed at right angles to the split reset rows, columns, or diagonal lines of mirrors.
However, the use of a split reset mirror addressing scheme does allow operation with smaller bit display intervals without the penalty of optical dead time, and there is thus greater freedom for manipulating the displayed bit sequence in order to minimise artefact generation. Thus, overall, the advantages of split reset operation outweigh the disadvantages.
Once an optimumised bit weight sequence has been determined according to GB93/02129 so as to minimise image artefacts on a non-split reset type display, the degree of artefact degradation of a split reset type display can, in principle, be reduced by displaying the same bit weight sequence on each of the split reset rows. This is feasible until the total time required to load the data latch and reset the mirrors for all the reset rows exceeds the bit weight display duration. Once this occurs, then at some point within the bit load cycle, the same mirror reset cycle will be required to load and reset two rows of mirrors simultaneously in order to terminate the current bit on one row and start the equivalent bit on another row.
Furthermore, for an N row reset scheme, the total time required to load the data for all N rows will be the same as for the non-split reset case, that is the total time is limited by the DMD input data bus bandwidth. However, because the single data load and mirror reset of a non-split reset scheme has been converted into N separate data loads and mirror resets, the total mirror reset time for a split reset scheme will be increased by a factor N. Thus, a split reset system of the form disclosed in U.S. Pat. No. 5,673,060 will have a longer overall single bit load/mirror reset cycle time than the equivalent non-split reset system, and hence will have a degraded motion induced artefact performance.